Design and Analysis of Gate-Stack 7 nm node Tri-gate FinFET for low power Application

A novel 7 nm node gate-stack tri-gate n-channel FinFET with multiple oxide layers is explored in this paper. The device is designed and analyzed using technology computer-aided design (TCAD) simulations to examine the accuracy of results at lower gate lengths. The effect of oxide degradation for low-k dielectric is overcome by considering gate-stack oxide consisting of both low and high-k oxide layers. The proposed device shows suitable short channel electrical characteristics such as drain-induced barrier lowering (DIBL), subthreshold swing (SS), and on-current to off-current ratio (I
ON
/I
OFF
) even at such a lower gate dimension. An excellent I
ON
/I
OFF
ratio of 107 and SS value of 100 mV/dec are obtained with DIBL calculated to be 83 mV/V.