Settling time minimization in PLL frequency synthesizers

To minimize the frequency settling time, an attempt to optimize the parameters of the 3/sup rd/ order PLL frequency synthesizer (FS) is described in this paper. Using the quasi-continuous analysis, the analytical expressions for calculating the suboptimal ratios of parameters for the loop filter are derived, expecting the linear transfer characteristic of phase-frequency detector (PFD), and constant gain of the voltage controlled oscillator (VCO). The proposed analytical results can serve as the basis for optimizing the low pass filter (LPF) parameters to ensure the fastest frequency switching process in the PLL FS at a predicted value of the residual frequency error. For practical use, the impact of parameter tolerances to the actual settling time is considered. It is shown that the minimum settling time is considerably sensitive to the values of the LPF component parameters.