ADC-Less Reprogrammable RRAM Array Architecture for In-Memory Computing

Nonvolatile memories, such as resistive random access memory (RRAM), for in-memory computing (IMC), have shown great potential in accelerating neural networks (NNs). However, existing IMC architectures rely on the area and power-hungry analog-to-digital converters (ADCs) for sensing the current, diminishing all the benefits of RRAM. Also, enhancing memory density is essential for implementing compact and efficient artificial intelligence (AI) systems. Implementing multiple states in a single memory cell decreases the resistance between states, making it difficult to sense the current. Thus, incorporating ADCs in multilevel cells (MLCs) further increases the design cost. This article proposes an ADC-less reprogrammable RRAM-based IMC architecture. The ADC-less sensing scheme converts the RRAM array current into its digital equivalent. The proposed scheme can distinguish RRAM resistive states equivalent to 4-bit/cell with a minimal resistance margin of 0.3
$\text{K}\Omega $
between two consecutive states. It is realized with only 12 transistors, the least among the state-of-the-art designs used in IMC architectures. This article also presents an MLC programming method, resulting in a 22% cycle-to-cycle and device-to-device variation-tolerant design with an average power consumption of
$21.5 ~\mu \text{W}$
, which is 60.18% less than the contemporary IMC architectures. Furthermore, the proposed current sensor (CS) requires only 12 transistors which is the least among the state-of-the-art works.