Effect of Back-Gate Dielectric on Indium Tin Oxide (ITO) Transistor Performance and Stability

Amorphous oxide semiconductors (AOSs) are receiving increased attention for electronics requiring low fabrication temperatures, but concerns remain about their stability. Here, we fabricate thin (~4 nm) indium tin oxide (ITO) field-effect transistors (FETs) with three back-gate dielectrics (HfO2, Al
$_{{2}} \text { O}_{{3}}$
, SiO2) deposited under various conditions. We find that low dielectric surface roughness < 1 nm ensures good ITO channel mobility, high dielectric breakdown field, and reduced trap states as confirmed by our simulations. The FET subthreshold drain current is accurately described by incorporating both interface and ITO bulk donor traps into the simulations. We also study the ITO devices under positive bias stress (PBS), finding the highest stability with HfO2 dielectrics, which contrasts reports on other AOS transistors. Through benchmarking, we identify lowering the equivalent oxide thickness (EOT) as one of the major contributors for improved PBS stability. These findings elucidate several key parameters for the improvement of AOS FET performance and stability.