Analysis of Quarter Method Applied ROM-Based DDFS Architecture

This paper compares various performance metrics of the conventional direct digital frequency synthesis (DDFS) with DDFS introducing the quarter method, which is most commonly used among ROM-based DDFS. The evaluation is implemented at the register-transfer level (RTL) in the low-power and general-purpose 65 nm CMOS technologies, and 180 nm CMOS technology. We have observed that phase-to-amplitude converter (PAC) becomes a key building block that mainly determines the performance of DDFS. At a 12-bit resolution, the PAC of the conventional DDFS occupies about 97% of the total cell area and accounts for approximately 83% of the total power consumption. On the other hand, the PAC of DDFS with the quarter method applied occupies about 80% of the total cell area and uses about 45% of the total power consumption. In addition, because the quarter method requires additional decoding logic to map the phase to the corresponding amplitude, this method has area and power consumption disadvantages at relatively small resolution targets below 10-bit. However, at relatively high-resolution targets beyond 11-bit, the quarter method has significant benefits in terms of various performance metrics (e.g., area, power consumption, and speed). Then, the quarter method has advantages at resolutions exceeding 7 bits based on figure of merit (FoM). Based on FoM, a similar pattern is evaluated despite changing the CMOS technology. As a result, the quarter method is the crucial structure in DDFS architecture. The designed DDFS is verified in implementation results using a field programmable gate array (FPGA) in 65 nm CMOS technology.