ESD mitigation for 3D IC hybrid bonding

Three-dimensional (3D) die-stacking has become a promising way to continue improving the integrated circuits performance. However, the risk of electrostatic discharge (ESD) during the stacking process is not yet fully understood. In this paper, we focus on understanding the electrostatics before the contact moment for the 3D stacking process. Our findings indicate that the stacking process presents a relatively low risk of ESD.