Cryogenic Measurement of CMOS Devices for Quantum Technologies

In this article we present the experimental characterization of active components of a standard 65 nm CMOS technology for a temperature range from 313 to 5 K, analyzing the variation of the main parameters over temperature and voltage, recovering their main parameters (threshold voltage
$V_{\text {th}}$
, transconductance
$G_{m}$
and channel conductance
$G_{\text {DS}}$
). The measurement has been carried out wire-bonding the bare dies with the devices to a dedicated printed circuit board (PCB) that has been placed inside a dilution refrigerator. The
$I_{D}$
-
$V_{\text {DS}}$
curves for both NMOS and PMOS transistors shows an increase of
$I_{D}$
in the cryogenic regime that is more relevant for high values of
$V_{\text {GS}}$
because for lower values it is partially compensated by the variation of
$V_{\text {th}}$
. Also, a kink is observed in these curves for high
$V_{\text {DS}}$
values, caused by the bulk current generated by impact ionization at the drain combined with the increased resistivity of the frozen-out substrate. The transconductance
$G_{m}$
reaches non-zero values for higher
$V_{\text {GS}}$
as
$T$
decreases and then peaks to higher values in the cryogenic regime. In turn,
$G_{\text {DS}}$
increases for increasing
$T$
, following the behavior observed for
$I_{D}$
. Both results are in accordance with other thermal characterizations carried out on CMOS transistors in different technologies.