Reliability Concerns of TSV-Based 3-D Integration: Impact of Interfacial Crack

The demands for improved performance, lower cost, and better signal integrity in 3-D packaging technology led to the development of through silicon via (TSV). However, TSV fabrication, testing, and services primarily induce undesirable thermomechanical stress during thermal cycling. It initiates microcracks (popularly known as interfacial cracks) across interfaced layers of TSV due to a coefficient of thermal expansion (CTE) mismatch. This article for the first time presents a comprehensive analysis of via parasitic that adversely affects the electrical characteristics of TSVs considering the heating and cooling scenario of interfacial cracks. It comprises a novel equivalent electrical circuit that includes fault modeling as well as reliability concerns in terms of crosstalk-induced delay, power dissipation, energy release rate (ERR), and S-parameter. The metal–oxide–semiconductor (MOS) effect is considered to model the via faults at various crack widths. Using a CMOS-based driver-via-load setup at 32-nm technology, the proposed electrical model is used to analyze the crosstalk, power, and losses considering both the heating and cooling modes. A closer validation of the obtained results demonstrates a good agreement with the experimental data for an approximate deviation of 2.5% in the scattering parameter. Furthermore, it is elucidated that the cooling mode is 14.58% more vulnerable than the heating in terms of power delay product (PDP) by considering height and crack width of 9.6 and
$1.79 ~\mu \text{m}$
, respectively.