An Innovative Program Scheme for Reducing Z-Interference in Charge-Trap-Based 3-D NAND Flash Memory

In this brief, we propose an innovative program scheme to mitigate
${z}$
-direction interference (
${Z}$
-interference) in charge-trap-based 3-D NAND flash memory. Our approach adjusts the position of trapped electrons in charge trap nitride (CTN) layer during the program operation by varying the pass voltage (
${V} _{\text {pass}}$
) on both side word lines (WLs) of the selected WL. Specifically, cells with a high threshold voltage (
${V} _{\text {th}}$
) place electrons in the program direction, whereas cells with a low
${V} _{\text {th}}$
place electrons in the opposite direction. Depending on the program-verify (PV) level pattern of the aggressor (Agr)-victim cell (Vic), the effective gate pitch can be modified, even though the physical gate pitch is fixed. We validate our proposed scheme using technology computer-aided design (TCAD) simulations and experimental measurements.