Physical and System Level Power Reduction Technique for NoC Architectures: Overview of State of the Art

Power dissipation and energy consumption are key factors for the performance improvement of modern technology systems. In recent years, several strategies have been proposed to solve the power management issues on embedded systems. In this paper, we classify the state of the art of those techniques. Classification is done based on run-time, activation, and idle state of the different components of the network on chip (NoC). We illustrate the requirement of power management based on several important parameters. A highlight is put on the drawbacks and benefits. Also, classification is done based on different NoC abstraction levels. However, by this paper, we intend to guide the researchers and application developers in getting insights about the strategies of power management techniques that will lead to the design of more efficient high performances in embedded systems of the future.