A Device-Circuit Aging Simulation Framework Integrating Trap-Based Models and Sensitivity Analysis for FinFET Technology

This work introduces a simulation framework for evaluating device and circuit aging, aiming to enhance reliability-aware designs. The framework integrates device aging analysis and circuit performance prediction, employing a modified time evolution method. Specifically, a novel trap-based FinFET reliability compact model is employed in the aging simulations, accommodating traps of various physical origins in negative bias temperature instability (NBTI). To improve the efficiency of predicting the long-term degradation, a new extrapolation method is implemented as an alternative to the traditional linear extrapolation technique. This method is derived based on the equivalent stress waveform and effective time. By mapping the device degradation to circuit performance metrics with the reliability-oriented sensitivity analysis, the device-circuit aging simulation results can be used to efficiently estimate the degraded circuit performance. The validity of the proposed reliability compact model and the fast extrapolation algorithm is demonstrated using nonradiative multiphonon (NMP) theory-based numerical simulations, along with experimental NBTI data on 7 nm pFinFETs. The framework is implemented in the circuit simulators via the open Model Interface (OMI), showcasing applications in multiple logic circuits.