A High-Level Methodology to Evaluate and Optimize Digital Architectures Targeting Spike Encoding

Spiking Neural Networks (SNNs) are promising candidates for low-power and low-latency embedded artificial intelligence. However, those networks require event-based data produced by neuromorphic sensors which are not widely available, except for a few specialized devices like neuromorphic retinas. For other data types, a solution lies in the use of conventional sensors in conjunction with encoding layers. However, when performed in software, this solution can be detrimental to energy consumption or latency. Here we introduce a flexible design methodology for efficiently implementing, optimizing, and evaluating digital architectures of spike encoding integrating algorithms available in the literature. In order to quickly evaluate different hardware architectures and to tailor the solution to the application needs, our approach relies on High-Level Synthesis (HLS) tools and Python scripting. We illustrate the methodology by generating various digital architectures of two encoding algorithms taken from the literature and we evaluate their energy consumption and timing performances on Field Programmable Gate Arrays. This work could overcome the lack of neuromorphic sensors and accelerate the development of lower-power hardware SNNs.