Manufacturability Evaluation of Magnetic Tunnel Junction-Based Computational Random Access Memory

The conventional computer architecture suffers from the memory bottleneck issue because of the physical segregation of logic and memory components. A new in-memory computing paradigm, called computational random access memory (CRAM), is proposed to address this fundamental limitation. It is not only a memory, but also capable of computing. Logic operations can be performed inside the CRAM array and by the memory cells themselves while the data never have to leave the memory array to be involved in computation. CRAM can be built based on non-volatile emerging memory devices, such as magnetic tunnel junctions (MTJs) or memristors. Benchmarking shows that CRAM is competitive for data-intensive, memory-centric, or power-sensitive applications in terms of performance and energy efficiency. In our recent work, an MTJ-based CRAM array hardware has been experimentally demonstrated. With these experimental inputs, we developed a suite of modeling of CRAM to capture its logic operation error rates. This metric is critical for evaluating the feasibility of CRAM for applications. In this work, by including a model of device-device size variation, we study the impact of device-device size variation of MTJs on the CRAM logic operation error rate and evaluate the manufacturability of CRAM accordingly. The modeling and results outline the manufacturability requirements of CRAM for a given set of error rate requirements, which can be further correlated to a specific application.