3.6-pJ/Spike, 30-Hz Silicon Neuron Circuit in 0.5-V, 65-nm CMOS for Spiking Neural Networks

In large-scale neuromorphic systems, a spiking neural network (SNN) provides a promising solution for energy-efficient computing. Optimizing SNN building blocks like neurons and synapses can further enhance computing efficiency. Due to their simplicity and computational efficiency, integrate-and-fire neuron (I&F) models are widely used in SNNs. In the past proposals of I&F neuron models, the main issue is the short-circuit currents in CMOS inverters, which significantly inhibit the circuit’s optimal performance and energy efficiency. This brief presents an energy-efficient differential-pair integrator (DPI) based I&F silicon neuron (SiN) circuit by utilizing the subthreshold source-coupled logic (STSCL) circuit topology as a replacement for CMOS inverters and incorporating a low supply voltage to mitigate leakage currents effectively. The proposed SiN is implemented in
$65 \textbf {nm}$
CMOS technology with a supply voltage of 0.5-
$\textbf {V}$
and has an energy consumption of
$3.6 \textbf {pJ}$
/spike with a spiking frequency (rate) of 30 Hz.