An Artificial Bee Colony Based Mapping Method for Three Dimensional Network-on-Chip

The total number of cores on a single chip is increased due to the rapidly decreasing size of transistors. In order to meet the performance demands of these designs, many designers prefer to use three-dimensional network-on-chips (3D-NoCs). These designs are good alternatives to traditional mesh structures since they consume less energy, ensure better performance, and need less area. However, new design algorithms are needed to map a given application to 3D-NoCs. In this paper, we propose an Artificial Bee Colony (ABC) based method for mapping application cores to the 3D-NoC architectures. We represent each possible solution with a different food source which produces a computed energy consumption. We aim to reduce the total energy consumption of the system. We compare our results against an existing study through several multimedia benchmarks in terms of the total energy consumption of the system. Our proposed approach produces comparable results in less time to an integer linear programming (ILP) based model which generates the optimum solution in a very long time.