Challenges in Precision Continuous-Time Delta-Sigma Data Converter Design [Feature]

We describe challenges encountered in the design of continuoustime delta-sigma modulators that target high resolution (>16 bits) over wide bandwidths (several hundreds of kHz). The linearity of the feedback DAC and flicker noise introduced by the loop filter are primary problems that need to be addressed. We describe two techniques that are inherently more linear than prior-art DACs, namely the virtual-ground-switched resistor DAC and the zapped virtual-ground-switched dual return-to-open DAC. Flicker noise can be eliminated by chopping, but one needs to pay careful attention to minimize chopping artifacts. Example multi-bit and singlebit designs achieving in excess of 100 dB SNDR over a 250 kHz bandwidth, designed in a 180 nm CMOS technology, are used to illustrate the efficacy of the techniques described in this article.