SET Tolerable SRAM Hardened by DMR Circuit With Feedback-Split-Gate Voter and High-Speed Hierarchical Structure

The scaled process technology and the increased operational frequency deteriorated the stability of the Static Random-Access Memory (SRAM) working in the harsh radiation environment, partially due to the Single Event Transient (SET) inducing operational failure. As analyzed in the brief, the SET induced “0-1” upset at the word-line (WL) is the crucial operational failure reason. A Feedback-Split-Gate (FSG) voter without delay penalty at the output is proposed to migrate the SET generated in the decoding array. The FSG-voter with less logic effect reduces path effect of the decoder hardened by Double Mode Redundancy (DMR). SET-sensitive area of the decoder is reduced as a result. A new local reading and writing structure with less latency is proposed to protect cells from SET induced disturbance. The correction coverage cost of the proposed peripheral circuit is 746% improved.