Design and Implementation of a Stack-based SoC Supporting Real-time Forth Operating System

Aiming to fully harness the performance of existing real-time Forth operating systems, a 32-bit stack-based SoC has been designed. The SoC is interconnected through the Wishbone bus, with the stack processor serving as the master device and peripheral devices as slaves. The arbitration method employed is round-robin. The stack processor is designed with a four-stage pipeline, and the instruction set is extended and improved based on the J1 instruction set. Experimental results reveal that at the maximum clock frequency, when compared to the stack processor currently supporting real-time Forth operating systems, the stack-based SoC exhibits significant enhancements in three crucial real-time performance metrics: maximal interrupt latency, task context switching time, and real-time task response time. These improvements are evidenced by achieving values of 2.36us, 1.42us, and 4.93us, respectively. As a result, the stack-based SoC effectively unleashes the capabilities of the Forth real-time operating system.