Design of Mixed-radix FFT Processor Based on The Modified CORDIC Algorithm

To address the problems of low computational flexibility and high hardware complexity of existing Fast Fourier Transform (FFT) processors, on one hand, this paper designs a Radix-2/4 Mixed FFT processor with a 5-stage pipeline structure, in which the first three stages are fixed Radix-4 butterfly units and the last two stages can be flexibly configured as Radix-2 or Radix4 butterfly units. On the other hand, this paper proposes a modified Coordinated FFT processor. On the other hand, a modified Coordinate Rotation Digital Computer (CORDIC) algorithm is proposed in this paper. Compared with the traditional CORDIC algorithm, the modified algorithm increases the convergence speed by $20 \%$ with the same computational accuracy by adding the non-rotation option and the step size definition of the lookup angle. The step size is reduced by half in turn. The hardware implementation reduces the hardware complexity by replacing the complex multiplication unit, which creates a lot of hardware complexity, with a modified CORDIC unit. The experimental verification and analysis conclude that this design can flexibly compute sequences of three lengths, 256, 512, and 1024, and the hardware area is reduced by $8.3 \%$ compared to the same type of design.