Point Multiplication ZigZag: An Optimized Co-Processor Architecture Design for SM2/3 Based on RISC-V

With the explosive growth of network information, demands for hardware implementation of cryptographic algorithms is increasing rapidly in recent years. However, the greatest limitation impeding extensive data encryption lies in that, there lack of efficient and lightweight cryptography implementations adaptable for ubiquitous smart devices, especially for those IoT devices, whose power and computations are both limited. In that case, a well-designed processing unit for cryptography computations is the critical way to boost ubiquitous usages of cryptography-based data protections. In this paper, we take SM2/SM3 algorithms as an example, to propose a brand new RISC-V compatible coprocessor design, named as ZigZag, aiming at easy usages in IoT environments. More specifically, we adopt two-fold optimizations for both SM2/3 computations on paralleled calculations in ZigZag, one is the paralleled double point multiplication design for SM2 computation acceleration, and the other is the optimization of SM3 in terms of message extension and compression functions. To justify the correctness and efficiency of the proposed ZigZag architecture, we implement a coprocessor prototype on the basis of RISC-V compatible development toolchains, running on Xilinx FPGA VCU118 when testing the prototype's performance. Our experiments show that, the ZigZag prototype takes 0.106 ms for a 256-bit point multiplication operation with 29.2k LUTs + 128 DSP hardware consumptions, which is 3.49 times faster in FPGA implementations than the state-of-the-art design.