Hardware Architecture of Channel Encoding for 5G New Radio Physical Downlink Control Channel

In this article, we propose a flexible and parallelizable hardware architecture of the channel encoding chain for the fifth generation new radio (5G NR) physical downlink control channel (PDCCH). We propose a new polar encoder architecture based on the radix-k processing and fast Fourier transform (FFT) concepts. We also introduce the hardware architectures for cyclic redundancy check (CRC) interleaver and rate matcher for 5G NR PDCCH. We synthesized this complete channel encoding chain on a Virtex Ultrascale+ field-programmable gate-array (FPGA) and show that with the proposed architecture, a codeword throughput of 4.26 Gbps can be realized while consuming as little as 3% of FPGAs resources. The proposed polar encoding architecture can encode from 84 up to 164 resource blocks in the 5G NR frame structure. Encoding of multiple resource blocks can be systematically applied to highly dense (time and frequency) 5G NR fronthaul links supporting multiple antennas.