Overview of methodologies for initial design of CMOS integrated circuits in deep submicron processes in different regions of inversion

This paper presents an overview and comparison of three popular methodologies used for initial sizing of analog CMOS circuits in deep submicron processes. The following methodologies are considered: design with models, based on the threshold voltage; design with simplified EKV models; design with the gm/ID methodology. The focus of the paper is on comparison of the accuracy of these methodologies when the design is performed in different regions of inversion of the transistor - weak, moderate and strong.