A 151.2-175.8 GHz Low Phase Noise LO Generator with Harmonic Enhancement Technique

In this paper, a low phase noise (PN) multiplier-based local oscillator (LO) generator working from 151.2 to 175.8 GHz with the third-harmonic enhancement technique is demonstrated in 65 nm CMOS process. The LO generator consists of voltage-controlled oscillator (VCO), doubler and buffer. The VCO employs a Class-F prototype with harmonic extraction and boosting technique to enhance the impedance and PN at the third-harmonic frequency. Meanwhile, by using the 4-bit switched capacitor bank and varactors, the LO generator achieves a tuning range of 15%. The simulated PN is -118.27 dBc/Hz at 10 MHz offset from 157.4 GHz, with an output power of -6.97 dBm. The figure-of-merit (FoM) is -184.09 dBc/Hz.