Enhancing Coverage of Clock Domain Crossing Assertion Verification leveraging Formal

Clock domain crossing (CDC) verification is an important and integral part of all system-on-chip designs. Static CDC verification uses structural analysis to identify missing synchronizers, potential glitch logic etc. While reviewing the generated violations, designers often overlook/assume certain facts about the design and waive the violations incorrectly. A single wrong assumption can cause downstream chip failure or critical function failure, which might lead to costly chip re-spins. Therefore, static CDC checks are not sufficient to guarantee the functional correctness of a design’s clock domains. CDC static verification tools typically have native assertion generation capability based on the crossing type to validate such designers’ assumptions. These assertions are subsequently leveraged by design verification teams to validate the assumptions made during static analysis. Achieving optimal functional coverage while verifying these assertions in simulation-based design verification (DV) is a major challenge due to the inherent incompleteness of simulation. In this paper, we propose a robust methodology for CDC verification by leveraging formal verification as a first step for verifying the static tool generated assertions and passing only the remaining assertions which could not converge through formal to simulation, hence reducing considerably the number of assertions to be targeted through simulation. This is turn can achieve a major left shift in CDC verification timeline, saving on time-consuming targeted testbench development which becomes the long pole. Also, assertions which are proved through formal are guaranteed to hold, improving the coverage and confidence of verification.