Pessimism Reduction in Voltage-Aware DRC using Simulation Results for Functionally Correlated Nets

With the advancement in VLSI manufacturing technology, it is possible to draw shapes very close to each other. While smaller spacing helps reduce the chip area, it has also made ICs vulnerable to reliability issues like a dielectric breakdown. Voltage-aware spacing rules are used to address these reliability concerns. The voltage-aware spacing rules are pessimistic due to static checking of rules that increase the spacing between wires, thus diminishing the benefit of the new process node. We present a methodology that removes the pessimism of voltage-aware spacing checks by using electrical simulation data in the physical layout. Traditionally physical design checks have been independent of electrical analysis of the circuit, and the use of electrical data during the physical side has brought many new challenges in the physical design flow. This paper presents a framework for using design topology and electrical simulation data during physical design, which DRC tools could leverage to perform less conservative voltage-aware spacing rules.