Design and Analysis of Charge Pumping Circuit for Low Power Charge Pump Based Phase Locked Loop Organization

In general the Charge pumping (CP) circuit is one of the major power consuming modules in charge pumping based Phase locked loop (CP-PLL) architecture. CP circuit transforms the voltage fluctuation in the Phase and Frequency detection circuit into equivalent current signal and supports in sustaining a steady control signal to retain the frequency of Voltage control oscillator (VCO). In this article a new CP circuit is proposed by using C2MOS logic. To construct the topology of anticipated circuit, the power saving practices such as lessening the counts of total MOS device usage and path splitting approaches are integrated, which leads to falling of switching and short circuit power dissipation correspondingly. The proposed CP model is executed in DSCH - MICROWIND tool and assessed by simulating the model at 0.12µm - 6 Metal model CMOS technology. The system level simulation indicates that the anticipated design attains power saving from 59% to 79% with minimum layout area occupation.