An Efficient High-Speed Architecture for Fast Fourier Transform using Pipelining

Fast Fourier Transform (FFT) is an effective approach for computing the Discrete Fourier Transform (DFT), it has been employed extensively in a variety of applications recently. For lengthy sequences of real-time data computing, the FFT becomes difficult and consumes more time. Therefore, a technique that can quickly compute the FFT for large sequences of input is essential. While pipelining can significantly improve processing speed, it introduces complexities that need to be carefully addressed. To overcome these challenges, designers need to carefully plan the architecture, conduct thorough simulations and performance analysis, and use appropriate optimization techniques. In this paper, the design to diminish the delay of the 8- point radix-2 Decimation-in-time is presented. The objective of the proposed design is to reduce the total delay using pipelining at different levels at certain positions that are used to compute the FFT. This can be attained by introducing pipeline registers across the feed-forward cutset. The speed of the FFT increases as the critical path is reduced. The critical path is reduced when pipelining is done as well as the latency is increased. Latency is defined as the difference in the data that is available in the sequence circuit and the output data that occurs first in the pipelined system. The prototype of an 8- point pipelined FFT is designed and simulated using Xilinx Design Tools Vivado ML Standard 2021.1. The 8-point pipelined FFT architecture at 2-level position 1 has obtained a reduced delay of 6.328 ns than unpipelined architecture respectively.