Thermal Stress Effect on 3D Integrated Circuit Performance and Reliability

The technology of the through silicon vias (TSVs) plays a significant role in 3D integrated circuits (3D ICs). TSVs have the ability to vertically facilitate enormous and short interconnects between stacked silicon dies to create 3D integrated circuits; thus, increasing their value and functionality. The fabrication of TSVs undergoes several stages and can be performed in different ways. However, the mismatch of the coefficient thermal expansion (CTE) between the material of TSV and silicon substrates has resulted in the accumulation of crack driving force and tensile hoop stress in the silicon substrate. In this paper, thermal stress, its effect on the 3D IC devices, and the solutions proposed in several studies to increase performance and reliability of 3D ICs were examined.