Application of Machine Learning in FPGA EDA Tool Development

With the recent advances in hardware technologies like advanced CPUs and GPUs and the large availability of open-source libraries, machine learning has penetrated various domains, including Electronics Design Automation (EDA). EDA consists of multiple stages, from high-level synthesis and logic synthesis to placement and routing. Traditionally, estimating resources and areas from one level of design abstraction to the next level uses mathematical, statistical, and analytical approaches. However, as the technology node decreases and the number of cells inside the chip increases, the traditional estimation methods fail to correlate with the actual post-route values. Machine-learning (ML) based methodologies pave a strong path towards accurately estimating post-route values. In this paper, we present a comprehensive survey of the existing literature in the ML application field in EDA, emphasizing FPGA design automation tools. We discuss how ML is applied in different stages to predict congestion, power, performance, and area (PPA), both for High-Level Synthesis (HLS) and Register Transfer Level (RTL)-based FPGA designs, application of design space exploration and application in Computer-Aided Design (CAD) tool parameter settings to optimize timing and area requirements. Reinforcement learning is widely applied in both FPGA and ASIC physical design flow, a topic of discussion in this paper. We also discuss various ML models like classical regression and classification ML, convolution neural networks, reinforcement learning, and graph convolution network and their application in EDA.