An FPGA-Based Training System for a 1T1R Memristor Array With 500 nS Conductance Resolution Limit

Brain-inspired computing is a key technology to break through the von Neumann bottleneck, and memristors have become potential candidate devices for achieving brain-inspired computing. The precise tuning of the conductance of a memristor device in the memristor array determines the accuracy of its pattern recognition. However, the existing commercial semiconductor parameter analyzers are not capable of training one-transistor-one-memristor (1T1R) memristor arrays. In this research, we propose a training system based on a field programmable gate array (FPGA) to precisely modulate the conductance states of the 1T1R memristor arrays. The system consists of a pulse generator with 20 ns resolution, a matrix switch and a resistance measurement unit, which can generate nanosecond pulses and automatically perform Forming, SET, RESET and READ operations on a
$32\times32$
scale 1T1R memristor array. The experimental results show that the system can map offline training data into memristor resistance values between 1
$\text{k}\Omega $
and 100
$\text{k}\Omega $
with a 500 nS conductance resolution limit. This system contributes to the investigation of the physical mechanisms of conductivity modulation in memristors, which improves the capability for future applications of memristors in high-density storage and high-precision neuromorphic brain-inspired computing.