Encoder Architecture for Systematic Polar Codes Using Single-Step Encoding Scheme

Systematic polar codes show better bit error rate (BER) performance than nonsystematic polar codes. However, the BER improvement of systematic polar codes comes at the cost of increased encoding complexity. It is highly desired to use the minimum storage units and XOR calculation units for the efficient hardware encoder design. The two-step encoding scheme is commonly used to implement systematic polar encoder, but this scheme does not have universality. For better generality, the encoder architecture implemented in this paper is based on a single-step encoding scheme. In this paper, a serial encoder architecture of the systematic polar codes using the latest low-complexity encoding algorithm is implemented. Moreover, two parallel architectures with 2-bit and 4-bit parallelism are also implemented. The synthesis results under the TSMC 28nm CMOS technology show that, compared with the serial architecture, the throughput of the encoder can be increased by 69.8% and 239.6% when using the 2-bit and 4-bit architectures, respectively. Besides, the 2-bit and 4-bit architectures keep similar areas compared to the serial one.