A Dedicated Memory Testing Processor Design

This paper presents a new dedicated processor design for Automatic Test Pattern Generation (ATPG) in Automatic Test Equipment (ATE). Instead of supporting only limited memory test algorithm, this paper proposes a dedicated processor which can process the instructions and generating variable memory test patterns in sequence. Both test patterns and pin mapping relationship are programmable, and can be easily adapted to a wide range of different topologic configurations of the memory array. The new designed instruction sets enable multiple Pattern Generators (PG) implemented inside the dedicated processors to work simultaneously and to generate test patterns up to 3.2Gbps automatically in line with microcode which test engineers have designed. This paper will describe in detail about the dedicated processor design and show the experiment results about flexible test patterns generation by microcode at high speed.