Data-Flow Modeling of SDRAM with Bank Group in Sequential Access with Intermittent Address Jumps Mode

As double data rate synchronous dynamic random-access memory (DDR SDRAM) iterations continue, the hardware response rate is unable to keep up with the increase in frequency. In order to fully utilize the bus, the Bank Group mechanism has been introduced into DDR SDRAM. DDR SDRAM itself, as a random-access memory, outputs data with suspension and randomness. The introduction of Bank Group has added new uncertainties to DDR SDRAM. The original data flow model of DDR SDRAM is no longer applicable to DDR SDRAM with Bank Group. In this paper, based on the original DDR SDRAM data flow model, we propose a data flow model for DDR SDRAM with Bank Group and derives a predictive formula for suspension time in response to the access characteristics of sequential access with intermittent address jumps mode, and its effectiveness and accuracy have been experimentally verified.