Multi-Level Pattern Synthesis Based on FPGA and DAC

This paper presents a design for a multi-level pattern generator based on Field Programmable Gate Array (FPGA) and Digital to Analog Converter (DAC). The proposed generator utilizes dynamic time error control to synthesize multi-level and pseudo-random bit sequence (PRBS) coding patterns, thereby expanding the application range of the pattern generator. To overcome the limited speed of FPGA logic resources and achieve a sample rate of 1.25 giga samples per second (GSPS) for the DAC, the design incorporates eight parallel channels of a processing unit. Experimental results demonstrate that the pattern generator can synthesize pattern signals at rates up to 120 mega samples per second (MBd) with voltage magnitudes of 2-level, 3-level, and 4-level.