Hardware Implementation of CABAC Decoder in HEVC Using HLS

In real-time Ultra High Definition (UHD) applications, video compression (VC) is essential. The H.265/HEVC standard is the newest of various VC algorithms available. In contrast to the predecessor AVC (Advanced Video Codec) standard, it can handle the UHD image at 120 frames per second. H.265/HEVC employs modern approaches like the sample adaptive offset (SAO) filter, inter- and intra-prediction, and CABAC entropy coding (Context-based Adaptive Binary Arithmetic Coding). In H.265/HEVC, CABAC is the sole entropy code that is employed. The computational complexity of CABAC decoding poses a significant challenge to achieving fast and efficient video decoding. This paper addresses this challenge by developing a hardware IP core for the HEVC video-coding standard that accelerates the CABAC decoding process, allowing real-time decoding of higher-resolution video streams. The proposed method uses the Xilinx Vitis HLS tool to generate RTL code for the CABAC decoder from a C++ implementation.