Ganged CMOS: trading standby power for speed

The authors present ganged-CMOS logic (GCMOS), a technique employing CMOS inverters with their outputs shorted together, driving one or more encoding inverters. These encoding inverters, serving to quantize the nonbinary signal at the ganged node, effectively buffer it from external circuitry, thus allowing locally smaller noise margins. As demonstrated by two novel adders, GCMOS achieves higher speeds and lower input capacitances than static CMOS, at the expense of higher static power dissipation. Monte Carlo simulations have shown that extremely tight process control is not needed to ensure correct operation; however, it is required to obtain optimum circuit performance.<
>