A FeFET In-Memory-Computing Core with Offset Cancellation for Mitigating Computational Errors

An analog In-Memory-Computing (IMC) core with offset cancellation is proposed in this work, where ferroelectric field-effect transistors (FeFET) are used as storage elements. Prior work indicates that FeFET IMC cores are able to achieve promising computation-and energy efficiency for accelerating multiply-accumulate (MAC) operations in artificial neural networks (ANN). However, it has been rarely discussed that IMC’s computational errors cause ANN’s inference accuracy loss. To address this problem, this work identifies the process variation of FeFETs and analog-to-digital converters (ADC) as the dominating error contributor to the computation accuracy based on numerical analysis. Inspired by the analysis result, this work suggests employing a dual-slope ADC with offset cancellation in the proposed IMC core to mitigate the FeFET-and ADC-induced computational errors. Because the offset cancellation needs to be performed only once as an initial step, the proposed method requires no extra computation step and energy consumption during computation. For lb-lb-(1-6b) MAC operations, the 2Snm prototype shows power efficiency of 2. S9TOPS/W to 15.4 TOPS/W at supply voltage of 1. 0V, and achieves 13.9 TOPS/W to 443 TOPS/W at an analog supply voltage of 0. 55V and a digital supply voltage of 0. 7V. The measurement shows an improved effective output resolution from 2 bits to 4 bits with the proposed offset cancellation, which reduces the average inference accuracy loss from 9.99% and 42.34% to 4.49% and 12.02% on the MNIST dataset under single-core and multi-core scenarios, respectively.