A Fully Integrated Adaptive Dead-Time Controlling Gate Driver Enabling ZVS in HV Converters

This work presents a gate driver with fully inte-grated adaptive dead-time regulation without additional external circuitry at the switch node. The driver makes use of an internal gate current measurement to infer the switch node voltage through the non-linearity of the SiC-FET’s reverse transfer capacitance. This enables high-frequency and high-voltage use cases without requiring costly HV components or bandwidth and performance limited HV processes. The proposed method does not incur additional losses, while also not limiting the dynamic driving ability of the gate driver. The proposed system has a resolution of 10ns and a dynamic range of up to 630ns. The gate driver is implemented in 180nmBCD.