Abstract:
This work proposes a continuous-time incremental zoom ADC with an on-chip 2^{\mathrm{n}\mathrm{d}}-order decimation filter. It adopts a 2^{\mathrm{n}\mathrm{d}}-order...Show MoreMetadata
Abstract:
This work proposes a continuous-time incremental zoom ADC with an on-chip 2^{\mathrm{n}\mathrm{d}}-order decimation filter. It adopts a 2^{\mathrm{n}\mathrm{d}}-order RT-DEM technique to eliminate DAC mismatch with a customized bidirectional circular shift register, and the quiet chopping technique to achieve high input impedance. The prototype ADC presents 91.6dB SNDR over an 88kHz bandwidth, consuming only 437\mu \mathrm{W} of power.
Date of Conference: 11-14 September 2023
Date Added to IEEE Xplore: 06 October 2023
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