A 40 kS/sCalibration-Free Incremental △Σ ADC Achieving 104 dB DR and 105.7 dB SFDR

High dynamic range (DR) Nyquist-rate ADCs are needed in many sensing applications. While noise-and mismatch-error shaping realize power efficient designs, they prevent true Nyquist-rate operation. We propose to combine variable-bitwidth operation and recuperation phase in an incremental Delta-Sigma modulator which allow to achieve intrinsic linearity combined with reduced quantization noise. The design achieves 105. 7dB SFDR and 104 dB DR over a 20 kHz bandwidth with $\mathrm{F}\mathrm{o}\mathrm{M}_{\mathrm{D}\mathrm{R}}$=180dB without calibration or randomization.