A 4-12.1-GHz Fractional-N Ring Sampling PLL Based on Adaptively-Biased PD-Merged DTC Achieving -37.6± 0.9-dBc Integrated Phase Noise, 261.9-fs RMS Jitter, and -240.6-dB FoM

This paper reports a fractional-N ring sampling phase-locked loop (FN-RSPLL). With the aid of our developed adaptively-biased phase-detector-merged digital-to-time converter, wideband loop bandwidth (LBW) tracking is achieved to keep the LBW almost constant within an ultrawide frequency tuning range (FTR) regardless of the supply voltage $(V_{DD})$ variation. Thus, this enables robust operating at the over-10-GHz frequency with wide FTR and large LBW for jitter suppression. Realized in a 40-nm CMOS, our FN-RSPLL measures the FTR from 4 to 12.1 GHz and scores 261.9-fs RMS jitter and 1.27-mW/GHz power efficiency corresponding to 240.6-dB FoM. The integrated phase noise and LBW over the FTR are -$37.6\pm 0.9\mathrm{d}\mathrm{B}\mathrm{c}$ and $34.4\pm 1.29\mathrm{M}\mathrm{H}\mathrm{z}$, respectively. The jitter varies by 18.8 fSRMS (7.4%) covering a 0.95-1.1-V $V_{DD}.$