First Foundry Platform Demonstration of Hybrid Tunnel FET and MOSFET Circuits Based on a Novel Laminated Well Isolation Technology

With a novel laminated well isolation technology for complementary tunnel FET (TFET) devices, this work experimentally demonstrates the first bulk Si TFET-based circuits and hybrid TFET-CMOS circuits based on a 300mm CMOS foundry platform. By utilizing the proposed DTCO workflow, the designed novel laminated isolation well for bulk TFET can successfully suppress the parasitic leakage current between adjacent TFET devices without area penalty. Both all TFET-based logic gates and SRAM cells are experimentally demonstrated and verified, indicating the validity of proposed well isolation technology. Moreover, benefiting from the proposed monolithic integration process with CMOS, there are no parasitic leakage current paths between adjacent TFET and MOSFET, enabling the first experimental demonstration of hybrid TFET-CMOS circuits including logic gates and 5-stage ring oscillator (RO). This work promotes the realization of high-energy-efficient and large-scale circuits based on TFET-CMOS hybrid foundry platform towards power- and cost-constraint AIoT applications.