Highly Secure Approximate Adiabatic Logic for Error Tolerant Applications

The switching activity and its resulting power consumption in real time VLSI applications is an important area of research currently. This becomes even more important when it comes to keeping the data secure from various attacks especially power. Many researchers explored that the adiabatic logic significantly contribute to avoid unwanted switching transitions happening in the digital circuits. It reuses certain energy which prevails the circuit to prevent power dissipation. In the proposed work, the focus is on designing energy efficient adiabatic arithmetic circuits to make it suitable for error tolerant applications. The 2:4 decoders are used as a fundamental block for designing full adders and comparators. Further, to make it suitable for error acceptable applications the proposed adiabatic circuit is finally approximated for reducing the complexity of the circuit and minimizing the power consumption. The approximation is done in the adder through true sum and true carry operation in which either sum or carry circuit is completely eliminated and obtained from inverting another. The proposed approach also helps in establishing application reliability, since security is a primary concern in data processing.