Layout Design Principle for Optimization of Transient Current Distribution among Paralleled SiC MOSFETs in Multichip Modules

This paper gives a layout design principle for multichip SiC MOSFET power modules taking the transient current distribution among paralleled dies into consideration. A few typical power module layouts are analyzed and modeled with parasitic layout parameters. With the analysis and comparison, a universal and practical design principle is proposed, which is to make the direction of parallel connections perpendicular to the direction of current flow. Applying this design principle mitigates the di/dt through the parasitic inductance between the source terminals of the paralleled dies. Furthermore, this approach avoids current coupling effects, which aggravate transient current imbalances. The design principle is verified with experimental results.