Investigation into Current Sharing of Parallel SiC MOSFET Modules using a Gate-Driver with Sub-Nanosecond Time-Skew Capability

This paper studies the current sharing behaviour of parallel-connected Silicon Carbide (SiC) modules, using a gate-driver capable of implementing sub-nanosecond delays between gate signals. The gate-driver is implemented with a central control unit complemented with programmable digital buffers to achieve a time-skew resolution of 0.5 ns. Results show the time resolution required to balance the current distribution in an experimental setup with four 1200 V/400 A SiC modules in parallel. Additionally, the potential of having a thermal runaway due to the current imbalance is analysed using the programmable delays to test the switch of the modules at temperatures up to 105°C.