Wide Common Mode LVDS Receiver Architecture Design and Analysis in 18nm FinFET Technology

The high-speed low-voltage differential signal (LVDS) I/O Receiver circuit design and analysis are presented in this work. The Problem identified as proposed design must support high speed LVDS data reception without any loss of data for input low swing with wide common mode range. The suggested LVDS receiver is compatible with the IEEE LVDS protocol. To accomplish the wide common mode voltage range of 0 - 2.4 volts, a receiver with a common-mode suppressor circuit is presented. It also includes a pre-amplifier to boost efficiency of power and give gain of voltage at high frequencies. Low power usage and high-speed signaling are two advantages of LVDS. Also, it doesn't have the significant overshoots and undershoots that high-speed rail-to-rail signaling systems do. Using the Cadence Virtuoso tool, the entire design is realized in an 18 nm (Fin Field Effect Transistor) FinFET process. The receiver operates with 3.2 Gbps data rate while consuming 6.805 mW of power and 3.780 mA of current. In this design transient analysis implemented with the aid of Eye diagrams, rise and fall delays, P2P fall/rise jitter is measured in low and high temperature ranges for Typical, Slow, and Fast corners with various common mode input signals. Using a 1.8V supply at a typical corner level, AC modelling yields a Gain of 20.7477. For different common mode voltage ranges, such as 100mV, 1.2V, and 2.3V, Monte Carlo simulations of duty cycle, rise, and fall delay characteristics were also tabulated. The proposed design achieved the targeted problem statement by supporting 0-2.4V wide common mode voltage range with high speed of 3.2Gbps compare to any other existing designs. Also, this proposed design supports different applications at different voltage levels.