Implementation of SC-FDE waveform on SDRP Using Vitis HLS

High Level Synthesis (HLS) tools give designers a time-efficient platform to develop the best design solution by exploring multiple design alternatives without a detailed understanding of hardware. In this work, hardware implementation of Single Carrier Frequency Domain Equalization (SC-FDE) waveform on software-defined radio (SDR) using Vitis HLS is presented. The SC-FDE waveform is implemented on an FPGA-based software-defined radio platform (SDRP). In this platform, Xilinx Virtex-7 FPGA is used as the main processing device to implement modulation, demodulation, synchronization, and Maximal Ration Combining (MRC) functionalities, and AD9364 transceiver is used for baseband to RF conversion. The waveform has been tested for AWGN and fading channels using the Channel Emulator. Resource utilization of HLS-generated IPs and performance of waveform is presented in terms of throughput and SNR with different channel conditions. Furthermore, the performance of this waveform with Xilinx LDPC IP is also presented. We have also validated waveform in the real scenarios by over-the-air transmission. The maximum throughput of 29 Mbps is achieved with this waveform.