Aspects of Enhancing Loop Band Width for FVF based LDO Regulators : An Intuitive Analysis

High band width (BW) and fast slewing are key to the faster time domain performance of the low drop-out (LDO) voltage regulators. Voltage buffers act as an essential stage in improving bandwidth (BW) and stability by moving the pole appearing at the gate of bulky pass transistor away from the operating band of interest. This method is traded off with the quiescent current requirement of an LDO in low power IoT applications, with a potential threat over the desired regulation owing to the low loop gain. In this context, the approaches of extending the BW with voltage buffers are explored, and analysed in comparison with the emerging technique such as: a voltage combiner. The theoretical intuitive analysis regarding the BW is formulated and a relative comparison of based on the simulation of output impedance is performed. Different topology of LDO designs are simulated in the 45nm CMOS technology for the BW investigations and additional design freedom provided by the combiner block is explained.