A Non-Blocking Multistage Interconnection using Regular Clock Schemes for QCA Circuits

Quantum-dot Cellular Automata (QCA) is a computing paradigm that uses Coulomb interactions to transfer information and execute logic without needing electric current flow. In QCA, wire crossings can be coplanar or multilayer. However, sudden changes in polarization levels can cause the system to enter a metastable state, leading to delays or incorrect processing. The tunneling mechanism of QCA basic units requires external clock signals to ensure changes occur adiabatically and at a desirable moment. This paper presents multistage interconnections that can minimize the overall area, encompassing the resources required for the wiring crossings. Furthermore, the proposed interconnection utilizes the regular USE clock scheme. Our design offers significant improvements over previous work. First, we achieve a 7.2× reduction in the multistage switch area. Additionally, our multistage QCA methodology could address the issue of wire crossing in multilevel QCA circuit design, yielding placement and routing solutions that closely approach the current state-of-the-art, even when employing a simple greedy approach.