AV1 Residual Syntax Elements Assessment and Efficient VLSI Architecture

Video coding is an essential technology that has become increasingly important as video usage has boomed in recent years. Video coding formats, or codecs, are constantly improved to support the need for higher compression ratios and different types of video content, which increases their complexity. In order to achieve the required bitrates, custom hardware design plays a critical role in video coding, as it can provide much faster execution than software-based alternatives. AV1 is a recent high-performance and open-source codec developed by AOMedia. The last step in its encoding flow is entropy encoding, which uses Syntax Elements (SEs) as input. Residual coefficients tend to compose the majority of the SEs. Therefore, the efficiency of the process that generates these SEs is essential for the performance of the entropy encoder. This paper introduces a novel circuit design for encoding the residual coefficients into SEs, the Residual Syntax Elements Generator (RSEG). Moreover, we present the results of a comprehensive statistical analysis of the residual symbols and the transform block sizes utilized by the AV1 codec. The synthesized RSEG, with 40 nm Bulk CMOS technology, indicates a power dissipation of 10.92 mW at 1.1 GHz and around 6.9k gates.